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15 hours ago
We are seeking an experienced Verification Engineering Lead to spearhead our pre-silicon verification efforts.
- Detailed expertise in SystemVerilog, UVM, and constrained-random verification.
- Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.
This role involves strategic planning, execution, and ownership of verification strategy for IP blocks, subsystems, or SoCs.
Key Responsibilities:- Develop and execute detailed verification plans for complex projects.
- Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
- Write and maintain directed and constrained-random test cases.
- Perform GLS (Gate-Level Simulation) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
- Collaborate with cross-functional teams to drive quality and coverage closure.
- Analyze functional/code/line/branch/coverage metrics and drive closure.
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
- 8–15 years of experience in ASIC/IP/SoC/Processor Design Verification.
- Proven track record in processor/microarchitecture verification, high-speed protocol verification, or GLS verification.
- Strong debugging skills and understanding of design specs and verification architecture.
- Proficient in scripting (Python, Perl, Shell, or Tcl) for test automation.
- Experience in ARM-based SoCs or RISC-V CPU verification.
- Familiarity with formal verification, LEC, or static verification tools.
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