Verification Engineering Lead

15 hours ago


Meerut, Uttar Pradesh, India beBeeVerificationEngineeringLead Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Job Title: Verification Engineering Lead

We are seeking an experienced Verification Engineering Lead to spearhead our pre-silicon verification efforts.

  • Detailed expertise in SystemVerilog, UVM, and constrained-random verification.
  • Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.

This role involves strategic planning, execution, and ownership of verification strategy for IP blocks, subsystems, or SoCs.

Key Responsibilities:
  1. Develop and execute detailed verification plans for complex projects.
  2. Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
  3. Write and maintain directed and constrained-random test cases.
  4. Perform GLS (Gate-Level Simulation) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
  5. Collaborate with cross-functional teams to drive quality and coverage closure.
  6. Analyze functional/code/line/branch/coverage metrics and drive closure.
Required Skills & Qualifications:
  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
  • 8–15 years of experience in ASIC/IP/SoC/Processor Design Verification.
  • Proven track record in processor/microarchitecture verification, high-speed protocol verification, or GLS verification.
  • Strong debugging skills and understanding of design specs and verification architecture.
  • Proficient in scripting (Python, Perl, Shell, or Tcl) for test automation.
Good to Have:
  • Experience in ARM-based SoCs or RISC-V CPU verification.
  • Familiarity with formal verification, LEC, or static verification tools.


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