Power Efficient Display Architect

3 days ago

Bengaluru, Karnataka, India beBeeRTL Full time US$ 1,04,000 - US$ 1,30,878
Display Subsystem Architect

This role involves leading the front-end development of Display Subsystem IPs, including complete RTL design cycles and collaboration with various teams.

Key Responsibilities:
  • Design leadership for Display Subsystem IPs.
  • Perform complete RTL design cycle: microarchitecture, coding, simulation, synthesis, STA, Lint, CDC, and low-power checks.
  • Collaborate with technology and circuit design teams to define and finalize IP specifications.
  • Partner with verification and physical design teams to ensure clean handoff and successful implementation.
  • Integrate Display IP into larger SoC platforms and support SoC teams during system bring-up.
  • Engage with software, test, and system teams to enable and validate low-power features.
  • Evaluate and implement new low-power techniques and technologies for power-efficient design.
  • Conduct performance analysis at block and chip level to identify bottlenecks and propose optimizations.
Qualifications:
  • 9+ years of hands-on experience in RTL design and SoC hardware development.
  • Strong domain knowledge in RTL design, integration, and front-end implementation.
  • Proficiency in RTL coding using Verilog, VHDL, and SystemVerilog.
  • Familiarity with EDA tools and flows.
  • Scripting skills in Perl, Python, or TCL for automation and flow customization.
  • Experience working in cross-functional and geographically distributed teams.
Preferred Skills (Bonus):
  • Prior experience with display technologies or subsystems.
  • In-depth exposure to display protocols and their integration.

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