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High-Speed Interface PHY IP Digital Design Engineer
1 month ago
We are seeking a highly skilled Digital Design Engineer to join our team at Qualcomm. As a Digital Design Engineer, you will be responsible for the design and development of high-speed interface PHY IP. This includes the implementation of SERDES high-speed interface designs, RTL development, and validation for linting, clock-domain crossing, conformal low power, and DFT rules. You will also work with the functional verification team on test-plan development and debug. Additionally, you will develop timing constraints, deliver synthesized netlists to the physical design team, and provide constraints support for PD STA. UPF writing, power-aware equivalence checks, and low-power checks are also part of your responsibilities. Furthermore, you will be responsible for DFT insertion and ATPG analysis for optimal SAF and TDF coverage. Finally, you will provide support to SoC integration and chip-level pre/post-silicon debug.
Requirements:
MTech/BTech in EE/CS with hardware engineering experience of 8+ years.
Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA.
Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable.
Experience with post-silicon bring-up and debug is a plus.
Able to work with teams across the globe and possess good communication skills.
Qualifications:
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
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