Senior Verification Engineer Position

6 hours ago


Anantapur, Andhra Pradesh, India beBeeVerification Full time ₹ 20,00,000 - ₹ 25,00,000

We are seeking a skilled professional to take on the challenge of senior design verification engineer. This is an excellent opportunity for individuals with expertise in SystemVerilog, UVM, and RTL DV.

Key Responsibilities:
  • Develop and execute test cases and regressions for DSP/Processor subsystems.
  • Perform performance analysis for DSP/NPU workloads.
  • Work on coverage closure, regressions, and debug at IP/Subsystem level.
  • Collaborate with architecture, design, and software teams.
  • Develop C-based verification flows along with SV/UVM-based environments.
Required Skills and Qualifications:
  • Strong knowledge of SystemVerilog & UVM.
  • C-based verification experience (processors).
  • Understanding of DSP architectures / Neural Network Engines (NNE).
  • Performance verification expertise (latency/throughput).
  • At least 4 years of IP/Sub-system DV experience.

This role offers a challenging career path with opportunities for growth and development. We are looking for a motivated individual who wants to be part of a dynamic team.

The ideal candidate will have strong expertise in SystemVerilog, UVM, RTL DV, GLS.

  • End-to-end Debug Subsystem Verification (trace, crash debug, visibility fabric).
  • Define and execute Verification Plans (VPlan).
  • Perform RTL DV, GLS, regression automation, and coverage closure.
  • Collaborate with SW & Architecture teams for debug feature validation.
  • Support ARM CPU debug infrastructure verification (CoreSight).
  • Strong in SystemVerilog, UVM, RTL DV, GLS.
  • Understanding of ARM CoreSight Debug Architecture.
  • ARM CPU debug methodologies (trace, crash debug).
  • Strong knowledge of C programming + scripting (Python/Perl).
  • At least 4 years of relevant verification experience.


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