Senior Verification Manager

2 days ago


Anantapur, Andhra Pradesh, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

Job Summary:

We are seeking an experienced Senior Verification Engineer to lead our Design Verification projects. This role requires extensive experience in ASIC/SoC Design Verification, with expertise in SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.

Responsibilities:
  • Manage the delivery of high-quality Design Verification (IP/Sub-System/SoC level) projects on time.
  • Develop verification strategies, test plans, coverage goals, and closure metrics aligned with industry standards.
  • Provide technical guidance in SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.
  • Collaborate with architects, designers, and DV engineers across global teams for seamless execution.
  • Lead multi-site DV teams, track progress, and mitigate risks through proactive planning.
  • Ensure adherence to best practices in verification and project management.
  • Drive continuous improvements in automation, regression efficiency, and verification productivity.

Requirements:

  • 14 to 20+ years of experience in Design Verification (IP / Subsystem / SoC level).
  • Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification.
  • Hands-on knowledge of AMBA protocols (AXI, AHB, APB) and Memory/DRAM verification flows.
  • Experience with Gate Level Simulation (GLS), Low Power (UPF), and Formal Verification is a strong plus.
  • Exposure to EDA tools such as Cadence Xcelium, Synopsys VCS, and Verdi.
  • Proven experience in project/program management, leading DV teams (10+ engineers).

About Us:

  • Opportunity to work on cutting-edge memory and SoC verification projects.
  • Lead high-impact DV programs with global exposure.
  • Collaborate with a technically strong, innovative team.


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