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2 weeks ago
We are seeking a highly skilled Principal IP/RTL Design Engineer for Ethernet Switch to join our team. The successful candidate will be responsible for designing and optimizing IP blocks (MAC, PCS, packet processors) for Ethernet switches.
- Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches.
- Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals.
- Optimize designs for low latency, high throughput, and power efficiency.
- Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control.
- Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation.
- Use P4 or related languages for programmable packet processing.
- Collaborate with teams for synthesis, timing closure, and IP integration.
- Document designs and stay updated on AI networking trends.
To succeed in this role, you will need:
- Education: BS/MS/PhD in Electrical or Computer Engineering.
- Technical Skills:
- Proficient in Verilog/SystemVerilog for design.
- Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control.
- Experience with InfiniBand, NVLink, or similar protocols.
- Proficiency in P4 or programmable data plane languages.
- Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE.
- Familiarity with power optimization or SDN.
- Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools.
- Soft Skills: Strong problem-solving, communication, and teamwork skills.
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