Senior Analog Layout Engineer
5 days ago
Job Title: Senior Analog Layout Engineer - FinFET Process Expert
About Us:
Cyient is a leading digital transformation and engineering solutions company. We are seeking a skilled Senior Analog Layout Engineer to join our team.
Salary: ₹1,200,000 - ₹2,400,000 per annum
Job Description:
We are looking for a seasoned Analog Layout Engineer with expertise in FinFET process design. The ideal candidate will have extensive experience in designing IO Layouts for advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, and 3nm.
Key Responsibilities:
- Design IO Layouts for critical blocks such as GPIO, SDIO, DDR IO, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, etc.
- Collaborate with cross-functional teams to integrate AMS IP into full-chip designs according to guidelines demanded by the Full Chip needs.
- Ensure timely and quality execution of Custom Layout design.
- Utilize industry-standard layout and verification tools in a Linux environment, including Cadence and Mentor EDA tools.
- Maintain a high level of knowledge and skills in Analog Layout concepts, including Matching, Electro-migration, Latch-up, Coupling, Crosstalk, IR-drop, Active and Passive parasitic devices.
Requirements:
- Minimum 4-15 years of experience in Analog Layout design.
- Hands-on experience with industry-standard layout and verification tools in a Linux environment.
- Excellent understanding of CMOS/Bi-CMOS/SOI/FinFET process.
- Experience in AMS IP integration in full-chip designs.
- Strong problem-solving skills in Routing Congestion, Physical Verification in Custom Layout.
Benefits:
We offer a competitive salary package, excellent benefits, and opportunities for professional growth and development.
How to Apply:
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