Principal Design Engineer
2 days ago
We are seeking a skilled Principal Design Engineer to join our team at Cyient, where you will play a key role in designing advanced IC layout for our global product R&D solutions.
With a strong focus on innovation and collaboration, you will work closely with our cross-functional teams to develop cutting-edge products from scratch. Your expertise in IO Layout design, particularly in advanced FinFET processes such as 16nm, 12nm, 10nm, 7nm, 5nm, and 3nm, will be invaluable to our success.
As a Principal Design Engineer, you will be responsible for:
- Designing high-quality IO Layouts that meet the stringent requirements of our customers
- Collaborating with senior engineers and architects to develop and implement new technologies
- Maintaining and improving existing design flows and methodologies
- Providing technical guidance and mentoring to junior engineers
To succeed in this role, you will need:
- Strong experience in IO Layout design, including GPIO, SDIO, DDR IO, and SERDES blocks (PHY, HDMI, PLL, ADC, DAC, LDO, etc.)
- Excellent understanding of CMOS, Bi-CMOS, SOI, and FinFET processes
- Knowledge of analog layout concepts, including matching, electro-migration, latch-up, coupling, crosstalk, IR-drop, and passive parasitic devices
- Ability to work effectively in a team environment and communicate complex technical ideas clearly
The ideal candidate will have a Bachelor's or Master's degree in Electrical Engineering or a related field and a minimum of 5 years of experience in IC design. We offer a competitive salary range of $120,000 - $180,000 per year, depending on location and experience. Benefits include comprehensive health insurance, retirement plan, and opportunities for professional growth and development.
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