Senior ASIC Design Engineer

3 days ago

Bengaluru, Karnataka, India beBeeRTLdesigner Full time ₹ 2,30,40,000 - ₹ 2,79,28,000
Job Summary

We are seeking a seasoned ASIC design engineer with expertise in RTL implementation to join our display subsystem team.

The ideal candidate will lead front-end RTL design and development of next-generation display subsystems, collaborating with cross-functional teams across geographies to ensure high-quality and power-efficient IP integration.

  • Design leadership for front-end development of Display Subsystem IPs
  • Perform complete RTL design cycle: microarchitecture, coding, simulation, synthesis, STA, Lint, CDC, and low-power checks
  • Collaborate with technology and circuit design teams to define and finalize IP specifications
  • Partner with verification and physical design teams to ensure clean handoff and successful implementation

Key Responsibilities:

  1. Integrate Display IP into larger SoC platforms and support SoC teams during system bring-up
  2. Engage with software, test, and system teams to enable and validate low-power features
  3. Evaluate and implement new low-power techniques and technologies for power-efficient design
  4. Conduct performance analysis at block and chip level to identify bottlenecks and propose optimizations

Required Skills & Experience:

  • Bachelor's or Master's degree in Electronics & Telecommunication Engineering, Microelectronics, Computer Science, or related fields
  • 9+ years of hands-on experience in RTL design and SoC hardware development

Technical Requirements:

  • Strong domain knowledge in RTL design, integration, and front-end implementation
  • Proficiency in RTL coding using Verilog, VHDL, and SystemVerilog
  • Hands-on experience in microarchitecture design for cores and ASICs

Soft Skills:

  • Strong communication and collaboration skills across time zones
  • Team player with a proactive approach to issue resolution

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