High-Performance AI Accelerator Designer
4 days ago
We are seeking a highly experienced Principal IP/RTL Design Engineer to contribute to the development of novel high-performance AI accelerators from scratch. In this role, you will collaborate with cross-functional teams to define and implement next-generation AI architectures.
The key responsibilities for this role include:
- Designing and implementing high-performance TPUs/MPUs and other related AI blocks using RTL.
- Ownning IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure.
- Optimizing design for power, performance, and area (PPA).
- Interfacing with physical design and DFT engineers for seamless integration.
- Driving design reviews, writing design documentation, and supporting post-silicon bring-up/debug.
Key qualifications for this role include:
- Bachelor's/Master's/Ph.D. in ECE/CS from a top engineering college with 5-15 years of relevant experience.
- Previous experience in either high-performance processor design or AI accelerator design is an advantage.
- Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts.
- Strong grasp of digital design fundamentals, computer architecture, virtual memory, and high-speed data-path design.
- Proficiency in Verilog/SystemVerilog and simulation tools.
- Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis.
This is a unique opportunity to work on cutting-edge technology and make a significant impact in the field of AI acceleration.
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