Lead Timing Closure Engineer

2 days ago


Nashik, Maharashtra, India beBeeTiming Full time ₹ 15,00,000 - ₹ 25,00,000

As a Specialist in Static Timing Analysis, you will be responsible for implementing complex System-on-Chip (SoC) blocks or full-chip designs from Register-Transfer Level (RTL) to Gate-Level Netlist (GDSII). Your primary focus will be on optimizing Performance, Power, and Area (PPA) while ensuring signoff closure.

Main Responsibilities:
  1. Fundamentals of Timing Closure: You will have expertise in timing closure fundamentals, including setup and hold analysis, clock domain crossing, and synchronization techniques.
  • Constraint Development and Maintenance Exposure: You will have experience with constraint development and maintenance, including the creation and implementation of design constraints to ensure successful synthesis and place-and-route operations.
  • DFT Modes in STA Timing Closure: You will understand how to utilize Design for Testability (DFT) modes in STA timing closure to optimize design performance and reduce errors.

In addition to these responsibilities, you will collaborate closely with our backend implementation team to ensure timely delivery of high-quality results. If you are passionate about VLSI/ASIC Design and possess strong technical skills, this role may be an excellent fit.



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