
Digital Circuit Verification Specialist
5 days ago
Are you looking for a challenging opportunity in design verification?
We have an exciting opening for a Design Verification Engineer. This role involves verifying complex digital circuits, ensuring they meet specifications and standards.
The ideal candidate will have hands-on experience with GLS tools like ZD/PAGLS/SDF/Scan dump verification. Strong debug skills, knowledge of UVM, System Verilog, and digital fundamentals are essential.
A strong understanding of timing simulation failures, setup and hold violations, low power aware verification, and scan dump verification is also required. Additionally, the candidate should be able to debug netlist functional failures.
The successful candidate will work on developing relevant test plans, utilizing scripts, System Verilog, UVM, and methodologies to increase the rate at which bugs are found and resolved.
Key Responsibilities:
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