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4 days ago
The successful candidate will have hands-on experience with full custom memory design and architectures, characterization, layout design, net-listers, and complete SRAM design verification at the compiler level.
- Populating and publishing execution plans, design quality plans, DFMEA, and project health reports
- Reporting risks and mitigation strategies
We are seeking a highly skilled professional who has expertise in the following areas:
- Memory Architectures: Good knowledge of different memory architectures is essential for this role.
- SRAM Design: Hands-on experience with SRAM leaf cell GDS from scratch to top-level integration is required.
- Physical Verification Flow: Expertise in working on memory layout design for advanced nodes (7nm/5nm/3nm) and proficiency in physical verification flow debugging (DRC, LVS, DFM, PERC, ERC, EM, IR) is necessary.
- Cadence Virtuoso and Synopsys Custom Compiler: Experience with Cadence Virtuoso layout editor and Caliber Physical Verification flow, as well as Synopsys Custom Compiler expertise, is a plus.
- Good Layout Practices: Understanding and working knowledge of good layout practices in lower process nodes is also essential.
- FinFET Architecture: Expertise in working on FinFET architecture and addressing challenges such as variability and manufacturability is required.
- Layout Optimization: Expertise in optimizing layouts for yield enhancement and manufacturing robustness is also necessary.
- Debugging Silicon Failures: Ability to perform debugging of silicon failures and identify layout-related issues is crucial.
This role requires 8+ years of experience. If you have the required skills and qualifications, we encourage you to apply.
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