Senior Analog Layout Design Engineer
7 days ago
At Micron, our vision is to transform how the world uses information to enrich life for all.
We are a world leader in innovating memory and storage solutions that accelerate this transformation. Our team of visionaries and scientists is developing groundbreaking technologies that are changing the way we use information.
Job Overview
We are seeking a Senior Layout Engineer in our DRAM Engineering Group in India. As a key member of our team, you will work closely with our global teams to design and develop critical analog blocks and full chip-level integration support.
About the Role
- Design and develop critical analog blocks, including temperature sensors, PLLs, ADCs, DACs, LDOs, and other complex circuits.
- Perform layout verification using Cadence VLE/VXL and Calibre DRC/LVS.
- Ensure timely delivery of high-quality block-level layouts.
- Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project milestones.
- Guide junior team members in their execution of sub-block-level layouts and review their work.
- Contribute to effective project management.
- Communicate effectively with engineering teams across the globe.
Requirements
- A minimum of 5 years of experience in analog/custom layout design in advanced CMOS processes.
- Expertise in Cadence VLE/VXL and Calibre DRC/LVS.
- Hands-on experience in designing critical analog blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, and other complex circuits.
- Good understanding of analog layout fundamentals, including matching, electro-migration, latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices, etc.
- Ability to understand design constraints and implement high-quality layouts.
- Excellent command and problem-solving skills in physical layout verification.
- Bachelor's or Master's degree in Electronic/VLSI Engineering.
Estimated Salary Range: ₹ 25,00,000 - ₹ 40,00,000 per annum
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