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7 days ago
We are seeking a skilled and motivated STA engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, focusing on performance, power, and area (PPA) optimization and signoff closure.
The ideal candidate will have expertise in timing closure fundamentals, constraint creation and maintenance, and DFT modes in STA timing closure.
- Timing Closure Expertise
Interested candidates can share their CV with the hiring manager.
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