Senior Digital Test Architect

2 days ago

Aurangabad, Maharashtra, India beBeeDft Full time ₹ 1,00,00,000 - ₹ 1,50,00,000

Job Description:

We are seeking a highly skilled and experienced DFT Engineer to join our team. The successful candidate will be responsible for developing and implementing DFT architecture for ASIC/SoC designs.

Key Responsibilities:

  • Design and develop DFT features, including scan chains, boundary scan (JTAG), MBIST, LBIST, and other test structures.
  • Collaborate with RTL and physical design teams to ensure seamless integration of DFT features.
  • Generate and validate test patterns using ATPG tools for stuck-at, transition, and path delay faults.
  • Perform fault simulation and coverage analysis to optimize test quality.
  • Support silicon bring-up and debug of test-related issues.
  • Work with ATE teams to develop test programs and support production testing.

Requirements:

  • Bachelor's degree in Computer Science, Electrical Engineering, or related field.
  • Minimum 3 years of experience in DFT design and development.
  • Strong knowledge of digital design principles, test methodologies, and ASIC/SoC design flows.
  • Excellent problem-solving skills, attention to detail, and ability to work in a team environment.
  • Proficiency in Verilog, VHDL, and other HDL languages.
  • Experience with DFT tools, such as ScanWorks, ModelSim, and Cadence.

Benefits:

  • Competitive salary and bonus structure.
  • Opportunities for professional growth and development.
  • A collaborative and dynamic work environment.

How to Apply:

Interested candidates should submit their updated resume to the email address provided below.

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