Digital Design Engineer

2 days ago

Bikaner, Rajasthan, India beBeeDftEngineer Full time US$ 1,25,000 - US$ 1,75,000

Key Responsibilities:

  • Define and Implement DFT Architectures
  • Plan, execute, and deliver Scan, ATPG, MBIST, and Boundary Scan Insertion and Validation.
  • Collaborate with EDA Vendors to Evaluate, Deploy, and Optimize DFT Tool Flows.
  • Automate Repetitive Tasks using Scripting to Improve Efficiency and Reduce Errors.
  • Support Test Vector Generation and Validation for Automated Test Equipment (ATE).
  • Provide Technical Guidance and Mentorship to Junior Engineers in the DFT Team.

Required Expertise:

  • Strong expertise in Digital Fault Tolerant architectures and methodologies.
  • Scan Insertion & Verification, ATPG (Automatic Test Pattern Generation), MBIST (Memory Built-In Self-Test), and JTAG / Boundary Scan.
  • Hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).
  • Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.
  • Solid understanding of System on Chip (SoC) design cycle, RTL to GDSII flow, and test requirements.

Desirable Skills:

  • Knowledge of low-power DFT techniques, including power-aware ATPG and retention flops.
  • Experience with post-silicon bring-up and ATE patterns.
  • Familiarity with safety-critical standards, such as ISO 26262 and DO-254.
  • Exposure to High-Speed IO testing, including SERDES and DDR.

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