
Senior Technical Lead for Design Verification Excellence
1 week ago
We are seeking a seasoned Design Verification Manager to lead our critical projects. This is an exciting opportunity for a technical leader to drive end-to-end project execution and team management within the Design Verification domain.
Key Responsibilities- Oversee Design Verification (IP/Sub-System/SoC level) projects ensuring timely, high-quality delivery.
- Develop verification strategies, test plans, coverage goals, and closure metrics in alignment with industry standards.
- Provide technical guidance in SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.
- Collaborate with architects, designers, and DV engineers across global teams to drive seamless execution.
- Manage multi-site DV teams, track progress, and mitigate risks through proactive planning.
- Conduct status reporting, milestone reviews, and client interactions.
- Mentor junior engineers and ensure adherence to best practices in verification and project management.
- Drive continuous improvements in automation, regression efficiency, and verification productivity.
- 14 to 20+ years of experience in Design Verification (IP / Subsystem / SoC level).
- Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification.
- Hands-on knowledge of AMBA protocols (AXI, AHB, APB) and Memory/DRAM verification flows.
- Experience with Gate Level Simulation (GLS), Low Power (UPF), and Formal Verification is a strong plus.
- Exposure to EDA tools such as Cadence Xcelium, Synopsys VCS, and Verdi.
- Proven experience in project/program management, leading DV teams (10+ engineers).
- Strong stakeholder management, planning, and execution skills.
- Excellent communication and leadership skills.
- Opportunity to work on cutting-edge memory and SoC verification projects.
- Lead high-impact DV programs with global exposure.
- Collaborate with a technically strong, innovative team.
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