
Senior Design Verification Engineer
18 hours ago
Job Overview
As a senior engineer in design verification, you will be responsible for developing and implementing testbenches to verify various IPs and/or SoCs.
Key Responsibilities:
- Design and implement simulation testbenches and low power simulation setup to meet target verification goals.
- Develop complex test benches in System Verilog using OVM/UVM methodology.
- Collaborate with cross-functional teams to develop test-plans, debug failures, and analyze coverage information.
- Have hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol.
- Experience in Low Power Simulation/UPF setup, debug low power simulation failures.
- Exposure to scripting languages like Perl, Unix shell or similar languages.
Requirements:
- 8+ years of design verification experience.
- MS (or higher) in EE/EC/ECC Engineering.
- Excellent knowledge of computer architecture and design verification fundamentals.
- Experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies.
About the Role
Mulya Technologies is a leading provider of AI-powered solutions across industries and global markets. We are seeking a talented individual to join our team as a senior design verification engineer.
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