Senior RTL to GDSII Design Flow Expert

Job Summary:We are looking for a highly experienced RTL Design Lead to drive the architecture, micro-architecture, and RTL development of digital IP/SoC blocks. The ideal candidate should have a solid background in RTL design using Verilog/SystemVerilog, along with experience in leading teams and interfacing with verification, DFT, and physical design...

Job Title: Lead RTL Design ExpertAbout the RoleWe are seeking a highly skilled and experienced RTL design expert to join our team. As a key member of our design group, you will be responsible for designing, verifying, and delivering high-quality digital designs that meet our customers' requirements.Key ResponsibilitiesDesign and verify digital circuits using...

Job TitleSenior RTL Design Engineers RoleCareer Overview:We are seeking highly skilled RTL Design Engineers.About the Role:The successful candidate will have experience in developing and verifying digital ICs using Verilog/System Verilog.Key Responsibilities:Develop and verify complex digital circuits using Verilog/System Verilog.Work closely with...

Senior RTL Design EngineersExperience : 3-5 yearsLocation : HyderabadStrong RTL(verilog/system verilog) skills with experience in IP development.• Ability to verify designs by writing simple testbenches.• Strong foundation in logic synthesis and timing closure concepts.• Good knowledge of SoC architecture, AXI bus protocols, hardware debug.•...

Senior RTL Design EngineersExperience : 3-5 yearsLocation : HyderabadStrong RTL(verilog/system verilog) skills with experience in IP development.• Ability to verify designs by writing simple testbenches.• Strong foundation in logic synthesis and timing closure concepts.• Good knowledge of SoC architecture, AXI bus protocols, hardware debug.•...

Senior RTL Design Engineers Experience : 3-5 years Location : Hyderabad Strong RTL(verilog/system verilog) skills with experience in IP development. • Ability to verify designs by writing simple testbenches. • Strong foundation in logic synthesis and timing closure concepts. • Good knowledge of SoC architecture, AXI bus protocols, hardware debug. •...

Senior RTL Design EngineersExperience : 3-5 yearsLocation : HyderabadStrong RTL(verilog/system verilog) skills with experience in IP development.• Ability to verify designs by writing simple testbenches.• Strong foundation in logic synthesis and timing closure concepts.• Good knowledge of SoC architecture, AXI bus protocols, hardware debug.•...

RTL Design EngineerExperience : 2-3 yearsLocation : HyderabadKnowledge in RTL Coding in Verilog or VHDLStrong understanding of Logic design, Digital design, System design aspects, FPGA flow, Design Constraints etc.Knowledge in Xilinx FPGA architecture and design flows like IPI, XDC etc.Good Knowledge in Tcl, Python scriptingInterested,please drop your...

Job Requirements Role Summary:Assist the STA team in checking timing quality of chip designs to make sure signals arrive at the right time and the chip works at the intended speed.Key Responsibilities:Support timing analysis of digital circuits using STA toolsRun timing checks like setup, hold, and clock skewWork with synthesis, placement & routing teams to...

Job Requirements We are seeking a highly skilled Senior RTL Engineer with 3-5 years of experience in RTL design. A Bachelor's degree in Engineering or related field is mandatory for this position. The ideal candidate will have a strong background in RTL design and a proven track record of success in this field. Key Responsibilities:- Design and implement...