
Expert Engineer for Advanced Circuit Designs
7 days ago
About this Role:
We are seeking a seasoned Lead Physical Design Engineer to assume ownership of Place-and-Route (PNR) for intricate flat SoC designs using advanced Cadence flow methodologies.
- Oversee physical design execution for complex flat SoC projects from RTL handoff through GDSII.
- Execute floorplanning, partitioning, power planning, and clock tree synthesis (CTS).
- Implement placement, routing, optimization, and sign-off using high-performance Cadence Innovus or equivalent tools.
- Develop and maintain SDC constraints for PNR stages.
- Drive physical verification (DRC, LVS, antenna checks) and resolve discrepancies.
- Perform congestion analysis and optimization for intricate flat SoC designs.
This position requires an in-depth understanding of Cadence flow, floor planning, CTS, routing, optimization, and sign-off closure. Proficiency with scripting languages such as Tcl, Perl, and Python is also essential.
The ideal candidate will have 10-12 years of hands-on experience in physical design and PNR, with a proven track record of handling intricate flat SoC designs in Cadence flow. Prior technical leadership or mentoring experience is also required.
Key Skills:
- Cadence flow
- Floor planning
- CTS
- Routing
- Optimization
- Sign-off closure
- Tcl
- Perl
- Python
What We Offer:
A dynamic work environment with opportunities for growth and professional development.
Collaborative team culture with experienced professionals in the field.
Competitive compensation package including salary and benefits.
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