Principal Hardware Architect

1 week ago

Mysore, Karnataka, India beBeeEngineer Full time ₹ 1,80,00,000 - ₹ 2,02,00,000
Senior Architect Engineer

 

Silicon Labs is the leading innovator in low-power wireless connectivity, merging cutting-edge technology into highly integrated SoCs.

 

This position involves developing complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture and multi-level caches, multiple clocks and resets, high-speed interfaces, peripherals.

 

The chosen candidate would need to contribute to, and manage a team for, the development of architecture, micro-architecture, and design of SoCs which include RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories, along with the integration of wireless systems, power management, and mixed signal IP.

 

The candidate would be responsible for leading a project through the entire product development process, including definition, planning, execution, and validation.

 

Responsibilities
  • Develop and execute Wireless SoC's from definition, through execution, and into production.
  • Define and plan the SoC requirements, providing necessary design collateral to support product approval gates.
  • Develop and maintain the SoC architecture or technical specification to meet product requirements, maximizing IP reuse.
  • Develop the design schedule, including milestones and resource requirements, coordinating with cross-functional teams on dependencies.
  • Coordinate with global design functional leads to track execution, triage issues, and perform prudent escalation.
  • Represent the design community, providing succinct weekly status, attending cross-functional meetings, and driving design action items to closure.
  • Perform SoC Design Integration, maintaining design collateral such as documentation, register libraries, and pinouts delivered to cross-functional teams.
  • Follow established quality procedures and processes to achieve first tapeout.
  • Support validation and product test teams during silicon bringup, validation, characterization, and qualification.
  • Triage, track, and resolve issues reported during silicon evaluation, executing metal or full layer revisions if necessary.

 

Requirements
  • 12+ years of industry experience.
  • Bachelor or Master's degree in Electrical or Computer Engineering.
  • Capable of leading complex IP, SOC development projects execution, with experience coordinating with contractors a plus.
  • Top-down planning and execution of SOC projects.
  • Experience in full-chip development cycle.
  • Able to build strong technical teams.
  • Hands-on experience in architecture, micro-architecture, digital design processes.
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI.
  • Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc.
  • Knowledge of processors like RISC-V and ARM processors.
  • Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure.
  • Knowledge of DFT including Scan, ATPG, MBIST.
  • Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling).
  • Knowledge of hardware accelerators.
  • Knowledge of Verilog and System Verilog.
  • Knowledge of scripting languages like Perl, Python, Tcl, shell.

 

Benefits & Perks
  • Equity Rewards (RSUs).
  • Employee Stock Purchase Plan (ESPP).
  • Insurance plans with Outpatient cover.
  • National Pension Scheme (NPS).
  • Flexible work policy.
  • Childcare support.

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