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Chief ASIC Design Timing Closure Specialist

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Alwar, Rajasthan, India beBeeTiming Full time ₹ 1,69,90,000 - ₹ 2,19,50,000
Job Summary

Lead the synthesis, static timing, and DFT efforts for an advanced mixed signal chip.

This highly visible role requires thorough knowledge of the ASIC design timing closure flow and methodology.

Key Responsibilities
  • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
  • Develop and maintain methodology and flows related to timing verification and closure
  • Generation of block and full chip timing constraints
  • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure
  • Support digital chip integration work and flows
About the Role

As a Staff Design Engineer/Design Manager, you'll be at the heart of the Soc design effort, interfacing with all disciplines and having critical impact in getting functional products to customers quickly.

You will work closely with our customers to define and set methodologies and design flows, utilizing your expertise in STA tools and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing.

Requirements

We're looking for someone with:

  • Expertise in STA tools and methodologies
  • Thorough knowledge of the ASIC design timing closure flow and methodology
  • Strong problem-solving skills and ability to analyze complex timing reports
  • Experience with digital chip integration work and flows
What We Offer

Join our team and grow your career in a dynamic and fast-paced environment. We invest in our engineers' growth and development, providing opportunities for them to continuously learn, both on and off the job.