
Chief Memory Architect
4 days ago
Job Overview
We are seeking a skilled Memory Design Engineer to join our team. As a key member of our design team, you will be responsible for designing and developing custom memory solutions, working on cutting-edge architectures, and collaborating with cross-functional teams to drive project success.
The ideal candidate will have hands-on experience in full-custom memory design and architecture, as well as expertise in SRAM leafcell GDS from scratch to top-level integration. Additionally, they will have experience working on memory layout design for advanced nodes (TSMC: 7nm/5nm/3nm) and proficiency in physical verification flow debug (DRC, LVS, DFM, PERC, ERC, EM, IR). Familiarity with Cadence Virtuoso layout editor and Caliber Physical Verification Flow is highly desirable.
Key Responsibilities:
- Designing and developing custom memory solutions
- Developing and implementing memory architectures
- Characterizing and verifying memory designs
Requirements:
- 8+ years of experience in custom memory design and architecture
- Hands-on experience in SRAM leafcell GDS from scratch to top-level integration
- Expertise in working on memory layout design for advanced nodes (TSMC: 7nm/5nm/3nm)
- Proficiency in physical verification flow debug (DRC, LVS, DFM, PERC, ERC, EM, IR)
Desirable Skills:
- FinFET architecture and challenges such as variability and manufacturability
- Address process-dependent effects like electro-migration (EM), IR drop
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