
High-Performance System Architect
1 week ago
As a Hardware Engineer, you will be part of an elite team responsible for the development of cutting-edge systems that power the quantum revolution and AI era.
Your Key ResponsibilitiesYou will lead the design and development of high-bandwidth, low-latency on-chip interconnects (NoC) and chip-to-chip interconnects, ensuring seamless integration into high-performance systems.
- Design and architect various interconnect topologies to meet bandwidth, latency, and reliability requirements.
- Develop architecture features and present proposed designs in high-level discussions.
- Collaborate with verification, DFT, physical design, FW, and SW teams to develop features.
- Ensure pre-silicon designs meet functional, area, and timing goals.
- Participate in silicon bring-up and validation of hardware.
PREFERRED EDUCATION AND EXPERIENCE
Master's Degree is required. 8+ years of relevant experience is also necessary.
- At least one generation of processor interconnect design delivery leadership (e.g., UPI, AXI, AMBA, NoC).
- Expertise in SMP coherency.
- Experience with different on-chip interconnect topologies (e.g., mesh, crossbar).
- Understanding of various snoop and data network protocols.
- Understanding of latency & bandwidth requirements and effective implementation means.
- Working knowledge of queuing theory.
- NUMA/NUCA architecture expertise.
- Proficient in HDLs - VHDL / Verilog.
- High-speed and power-efficient logic design experience.
- Collaboration with verification, validation, physical design teams for design closure, including test plan reviews and verification coverage.
- Good understanding of Physical Design and ability to collaborate with physical design team for floor planning, wire layer usage, and budgets, placement of blocks for achieving high-performance design.
- Leadership experience in uarch, RTL design teams for feature enhancements.
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