Verification Expert

14 hours ago

Meerut, Uttar Pradesh, India beBeeVerification Full time ₹ 80,00,000 - ₹ 1,50,00,000
Senior Design Verification Engineer

We are seeking an experienced Senior Design Verification Engineer to lead and contribute to the verification of complex IP blocks or SoC subsystems.

The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of driving verification efforts across multiple projects.

  • Lead and contribute to the verification of complex IP blocks or SoC subsystems.
  • Develop test plans, verification strategies, and coverage metrics based on design specifications.
  • Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM.
  • Collaborate with architects, designers, and other verification engineers to identify and debug design issues.
  • Develop and maintain verification infrastructure, scripts, and regression systems.
  • Perform functional and code coverage analysis, driving closure.
  • Provide technical guidance and mentorship to junior team members.
Required Skills and Qualifications
  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
  • 8–14 years of hands-on experience in ASIC/SoC verification.
  • Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa).
  • Solid understanding of verification methodologies, functional coverage, and assertion-based verification.
  • Experience in developing and maintaining testbenches from scratch.
  • Strong debugging skills and familiarity with waveform viewers like Verdi or DVE.
  • Good knowledge of scripting languages (Python, Perl, or TCL) for automation.
  • Familiarity with version control and CI/CD systems.
Preferred Qualifications
  • Experience in formal verification or emulation is a plus.
  • Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB).
  • Prior experience in leading a verification team or acting as a verification lead.
  • Exposure to post-silicon bring-up and validation.

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