Digital Circuits Testability Specialist

5 days ago

Kottayam, Kerala, India beBeeDesignForTestability Full time ₹ 25,00,000 - ₹ 40,00,000

Job Overview:

We are seeking an experienced Design for Testability (DFT) Lead to design and implement robust test solutions for complex digital integrated circuits.

  • DFT concepts such as scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis are essential.
  • Ambitious candidates should have hands-on experience in MBIST insertion and memory test validation.
  • Key expertise includes test mode timing constraints definition and knowledge in providing timing fixes/corrective actions for timing violations.
  • A strong background in scripting languages such as perl and shell is necessary.
  • Experience in RTL and gate-level simulations of scan and MBIST test vectors is highly desirable.
  • Familiarity with DFT rules in both RTL lint tool and ATPG tool is a must.
  • Knowledge of equivalence check and DFT DRC rules in Cadence Encounter Test is an added advantage.

The ideal candidate will have 7-15 years of experience in the field and excellent problem-solving skills. Strong communication and teamwork skills are also essential, along with good English proficiency. Adaptability in dynamic international team environments and quick adaptation to new tools and methodologies are key.

Requirements:

  • Minimum 7 years of experience in the field
  • Strong problem-solving skills
  • Excellent communication and teamwork skills
  • Good English proficiency
  • Adaptability in dynamic team environments

Bonus Points:

  • Expertise in RTL and gate-level simulations of scan and MBIST test vectors
  • Knowledge of Cadence Encounter Test

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