Senior Test Engineer
4 days ago
As a senior design verification engineer, you will play a crucial role in the development and implementation of SystemVerilog UVM-based testbenches for modem subsystems. Your primary responsibility will be to define and execute test plans from specifications, ensuring thorough end-to-end testcase implementation.
Key aspects of this role include:
Developing and owning SystemVerilog UVM-based testbenches for modem subsystems
Defining test plans from specs and driving testcase implementation end-to-end
Running regressions, analyzing failures, and ensuring functional & code coverage closure
Required Skills and Qualifications
To succeed in this position, you must possess strong ownership in modem/IP verification (4G/5G preferred), as well as hands-on experience in SV UVM verification. Key skills and qualifications include:
7+ years of hands-on experience in SV UVM verification
Strong ownership in modem/IP verification (4G/5G preferred)
Experience in writing testcases from spec and driving regressions
Expertise in both RTL and gate-level simulation
Good debugging and scripting (Python/Perl) skills
Nice to Have:
Achieving knowledge of wireless protocols (LTE/5G) would be beneficial, as well as experience with functional coverage closure and exposure to DFT/low-power verification.
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