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Engineering Design Verification Specialist

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Vijayawada, Andhra Pradesh, India beBeeVerification Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

Key Responsibilities:

  • Verify various IPs and/or SoCs as a member of the Design Verification Team.

About This Role:

We seek an experienced Design Verification Engineer to implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will be responsible for verifying various IPs and/or SoCs, including design validation and debug.

Required Skills:

  • Excellent knowledge of computer architecture and design verification fundamentals.
  • Experience with Verilog, popular EDA simulation, System Verilog assertions, and testbench methodologies.
  • Familiarity with AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol.
  • Hands-on experience in Low Power Simulation/UPF setup and debug low power simulation failures.
  • Prior experience with scripting languages like Perl, Unix shell or similar languages.

Achievement Guidelines:

  1. You must have at least 8 years of design verification experience, holding an MS (or higher) in EE/EC/ECC Engineering.
  2. A strong understanding of design verification principles is essential for this role.
  3. Able to work efficiently under deadlines, ensure results accuracy.

Please ensure that you can meet the following requirements:

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