Senior design verification engineer

3 weeks ago

Vijayawada, Andhra Pradesh, India Tessolve Full time

Job Summary:We are looking for an experienced IP/SOC Verification Engineer with a strong background in functional verification of complex digital IPs and So Cs. The ideal candidate will have expertise in System Verilog, UVM, and verification of standard protocols and processor subsystems. This role involves working closely with RTL designers and system architects to ensure robust, high-quality silicon.Key Responsibilities:Develop and implement block-level and top-level testbenches using System Verilog/UVM.Create detailed verification plans and drive the verification process from planning to coverage closure.Verify IPs and So C components including CPUs, memory controllers (e.g., DDR), interconnects (AXI/AHB/APB), and custom logic.Perform test case development, debugging, code coverage, and functional coverage analysis.Drive regression infrastructure and manage automated test environments.Collaborate with RTL designers, architects, and software teams to ensure functional correctness.Participate in design and code reviews, and provide feedback for continuous improvement of verification methodologies.Document verification results and support silicon validation teams, if needed.Required Skills & Experience:Minimum 5 years of experience in IP/SOC functional verification.Strong hands-on experience in System Verilog and UVM methodology.Proficient in testbench architecture, test case development, and coverage-driven verification.In-depth understanding of bus protocols like AXI, AHB, APB.Experience with processor-based So C verification (e.g., RISC-V, ARM, or equivalent).Exposure to DDR/LPDDR memory interface verification.Strong debugging skills using waveform viewers like Verdi, DVE, or Sim Vision.Familiarity with version control, scripting (Python/Perl/TCL), and simulation tools (e.g., VCS, Model Sim, Questa).Knowledge of assertions (SVA) and formal verification concepts.Good to Have:Experience in RISC-V architecture or working on open-source So C/IPs.Knowledge of cache systems, MMU, or peripheral subsystems.Exposure to FPGA prototyping, post-silicon validation, or emulation platforms.Familiarity with CI/CD pipelines and regression automation frameworks.

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