Chief Physical Design Architect

5 hours ago

India beBeeLeadership Full time ₹ 1,50,00,000 - ₹ 2,25,00,000
Job Overview

The Senior Physical Design Lead Engineer will be responsible for leading the physical design of complex ICs, with a focus on full-chip place and route (PnR) optimization.

This includes understanding of IO rings, package support, multi-voltage designs, synthesis, place and route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure.

Key Responsibilities
  • Independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM.
  • Participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM).
  • Well-versed with timing closure (STA), timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification.
  • Experience in lower tech nodes.
  • Good automation skills in PERL, TCL, and EDA tool-specific scripting.
  • Ability to take complete ownership for Block/sub-system for complete execution cycle.
  • Out-of-the-box thinking to meet tighter PPA requirements.

This role requires a strong understanding of complex IC design concepts, excellent leadership skills, and the ability to work independently with minimal supervision.

Required Skills and Qualifications
  • Expertise in physical design with a focus on full-chip place and route (PnR) optimization.
  • Understanding of IO rings, package support, multi-voltage designs, synthesis, place and route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure.
  • Experience with timing closure (STA), timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification.
  • Proficiency in PERL, TCL, and EDA tool-specific scripting.

Additionally, this role requires:

  • A minimum of 5 years of experience in physical design with a focus on full-chip place and route (PnR) optimization.
  • Proven track record of delivering high-quality designs on time and within budget.

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