Chief ASIC Physical Designer

3 days ago

India beBeePhysical Full time US$ 1,60,000 - US$ 2,20,000
Job Overview

We are seeking a seasoned professional to lead the physical design of next-generation ASICs that meet Engineering, Business, and Customer requirements.

Key Responsibilities:
  • Implement RTL to GDS2 flow.
  • Handle Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence.
  • Expertise in handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.
  • Perform Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off.
  • Identify complex technical problems, break them down, summarize multiple possible solutions.
  • Drive and hands-on flow development and scripting.
Requirements
  • 12+ years of professional experience in physical design, preferably with high-performance designs.
  • Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications.
  • Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
  • Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation.
  • Versatility with scripts to automate design flow.
  • Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams.
  • Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm.
  • Excellent physical design and timing background.
  • Good understanding of computer organization/architecture is preferred.
  • Strong analytical/problem-solving skills and pronounced attention to details.
Academic Credentials

BS or MS degree in Electrical Engineering or Computer Science. 10 years of experience in physical design role leading to an understanding of RTL to GDS development.

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