
Senior Physical Design Expert
2 weeks ago
Key Responsibilities:
- Develop and implement physical design solutions from RTL to GDSII.
- Plan, place, clock tree synthesize (CTS), and route complex circuits.
- Conduct static timing analysis (STA) and achieve timing closure.
- Run and debug physical verification checks (LVS/DRC/ERC) and power integrity assessments (IR Drop/EM).
- Collaborate with cross-functional teams including RTL, DFT, synthesis, verification, and packaging.
- Own PPA targets and meet timing goals.
- Participate in multiple tape-outs and manage block-level signoff closure.
- Automate and optimize flows using Tcl, Perl, Python, or shell scripting languages.
- Stay up-to-date with the latest EDA tools and technology trends.
Required Skills & Qualifications:
- Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related field.
- 4-10 years of experience in physical design with successful tape-outs.
- Strong expertise in Synopsys/Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, etc.).
- Deep understanding of digital design concepts, timing, and power trade-offs.
- Hands-on experience in advanced technology nodes (16nm and below preferred).
- Experience with scripting languages (Tcl, Python, Perl, Shell).
- Familiarity with ECO flows, DFT insertion, and low-power design techniques (UPF/CPF).
- Knowledge of signal and power integrity issues (IR/EM) is a plus.
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