Senior High Performance Engineering Professional

7 days ago

Thiruvananthapuram, Kerala, India beBeeHighPerformanceDesignEngineer Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
High-Performance Design Engineer Role

We are seeking a skilled High-Performance Design Engineer to lead our Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. This is a unique opportunity to leverage your expertise in STA tools, PNR tools, and SoC design flows to drive automation and validation of timing and physical design data across subsystem boundaries.

The ideal candidate will have a proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems. Experience with scripting languages such as Tcl, Perl, or Python for automating STA and PNR flows across multiple subsystem blocks is highly desirable.

In addition to technical skills, we are looking for a collaborative team player who can mentor junior engineers, foster technical growth, and share knowledge within the subsystem teams. Excellent communication skills are essential to present technical solutions and lead discussions with internal teams and customers.

Key Responsibilities:
  • Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
  • Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • Drive automation and validation of timing and physical design data across subsystem boundaries.
  • Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
  • Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
Requirements:
  • 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
  • Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.
  • Background in high-speed interfaces, or mixed-signal SoC subsystems.

This is an exceptional opportunity to join our team of experts and contribute to the development of cutting-edge technologies. If you are passionate about delivering high-quality results and driving innovation, we encourage you to apply.

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