Senior SOC Architectural Designer

12 hours ago


Bengaluru, Karnataka, India beBeeExecution Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
SOC RTL/DFX Execution Lead

We are seeking a highly skilled SOC RTL/DFX execution lead to join our team.

  • Lead and define overall test chip architecture, incorporating both functional and DFX aspects.
  • Integrate high-speed DDR PHY IPs into the test chip top-level RTL, necessitating expertise in DDR/LPDDR/HBM protocols.

About the Job:

Key Responsibilities:
  1. Define overall test chip architecture, incorporating both functional and DFX aspects.
  2. Integrate high-speed DDR PHY IPs into the test chip top-level RTL, necessitating expertise in DDR/LPDDR/HBM protocols.
  3. Develop custom logic at the test chip top level for interfacing and interacting with PHY IPs and associated logic.
  4. Implement SOC DFT features (TAP controller, JTAG/IJTAG, GPIOs, ESD structures) into RTL.
  5. Perform gate-level simulation using Synopsys VCS and Verdi.
  6. Develop SOC-level SDC and hand it over to PD.
  7. Contribute to UPF development and hand it over to PD.
  8. Translate ATPG patterns from IP level to SOC level and hand it over.
  9. Assist with Spyglass bringup and analysis for scan readiness/test coverage gaps.
  10. Run all SOC RTL QA checks (Lint/CDC/RDC/VCLP).
  11. Support silicon bring-up and debug.
  12. Develop efficient DFx flows and methodology compatible with front-end and physical design flows.
Requirements:
  • Bachelor's/Master's/Ph.D. in EE/ECE/CE/CS with a minimum of 10+ years of industry experience in SOC RTL/DFX execution, preferably with exposure to high-speed PHY or Serdes IPs design.
  • Experience with developing complete TestChip RTL, including integration of IEEE1149.1 TAP, GPIOs, etc., from early RTL design to post-silicon support.
  • Familiarity with MCM (multi-die integration into a package) is desirable.
  • Ability to integrate multiple IPs (with or without integrated JTAG controllers) into the testchip environment.
  • Knowledge of PLLs and DFX care-abouts is necessary.
  • Understanding of STA fundamentals and experience with SDC development.
  • Experience with UPF development.
  • Experience with translating ATPG patterns from IP level to SOC level.
  • Familiarity with SystemVerilog and UVM.
  • Strong problem-solving and debugging skills across various levels of design hierarchies.

Preferred Skills:

  • Multidisciplinary knowledge in digital IC design, signal integrity, and electromagnetic compatibility.
  • Familiarity with semiconductor manufacturing process and physics.
  • Working knowledge of Linux operating system.
  • Excellent problem-solving skills and ability to adapt to new technologies and tools.


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