
Lead Digital Circuit Designer
2 weeks ago
About the Position:
- Create detailed floor plans and perform complex partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI-aware routing, and timing analysis/closure for advanced low-power digital circuits.
- Develop and implement innovative designs using 65nm or lower node technologies with techniques such as Voltage Islands, Power Gating, and substrate-bias to reduce power consumption.
- Provide technical guidance and mentoring to junior Physical Design Engineers to enhance their skills and knowledge.
- Collaborate with front-end ASIC teams to resolve issues related to low-power design, voltage islands, power gating, substrate-bias techniques, and timing closure on DDR2/DDR3/PCIE interfaces.
- Maintain expertise in ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Have extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
- Possess a strong Physical Verification skill set and expertise in scripting languages such as PERL, TCL.
- Conduct Static Timing Analysis in Primetime or Primetime-SI to ensure efficient circuit performance.
Required Skills and Qualifications:
- Experience – 3 to 12 Years
- Excellent communication and documentation skills.
- Ability to interface with different teams and prioritize work based on project needs.
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