
Principal Digital Architect
16 hours ago
The Senior Design Engineer will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.
- Understanding of computer architecture and concepts is essential
- Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations
- Design verification experience: Sense amplifier analysis, self-time analysis and marginality analysis is required
- Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits
- Understanding of Power versus Performance versus Area trade-offs in typical CMOS design
- Strong knowledge of physical implementation impact on circuit performance
- High-performance and low power circuit designs with exposure to FinFet technologies, bitcell stability analysis
- Proven experience as the designated responsible individual for a memory design, leading a small team of designers
- Excellent interpersonal skills are expected
Circuit Design: Design and develop digital circuits for memory blocks like SRAM, register files, and caches. Simulation and Verification: Perform simulations and verification to ensure functionality and optimize for power, performance, area, timing, and yield.
Nice To Have Skills and Experience :
- Experience with Cadence or Synopsys flows
- Optimization of standard cells through Circuit Simulation
Requirements: 7+ years of experience in SRAM / memory design Margin, Char and its related quality checks
Skillset: Computer Architecture, Memory Compiler Development, Circuit Design, Simulation and Verification
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