Design Architect

2 weeks ago

Vadodara, Gujarat, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
About the Role

As a Design Verification Engineer, you will be responsible for verifying various IPs and/or SoCs within our Pre-Silicon DV Team.

Key Responsibilities
  • Implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
  • Develop complex testbenches in System Verilog using OVM/UVM methodology.
  • Assist with developing test-plans, debugging failures and analyzing coverage information.
  • Work with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies.
Requirements

To succeed in this role, you will need:

  • 8+ years of design verification experience.
  • MS (or higher) in EE/EC/ECC Engineering.
  • Excellent knowledge of computer architecture and design verification fundamentals.
  • Hands-on experience with AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol.
  • Experience in Low Power Simulation/UPF setup, debug low power simulation failures.
  • Exposure to scripting languages like Perl, Unix shell or similar languages.
  • Good written and oral communication skills.
Desirable Skills

A bonus would be experience with:

  • Assembly language programming.
  • PCEI MAC, OR USB MAC OR Bluetooth MAC OR Wifi 802.11 MAC layer protocol.

We are looking for a skilled engineer who can work independently or as part of a team.

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