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5 days ago
We are seeking a highly skilled Senior Design Engineer to lead the development of cutting-edge AI acceleration technologies.
Key Responsibilities- Design and implement high-performance matrix multiplication and low-latency interconnects for our next-generation AI accelerators.
- Develop optimized Verilog/SystemVerilog RTL for performance, timing, and area optimization.
- Implement high-speed data pipelines using AXI and NoC protocols.
- Orient designs towards high throughput, low latency, and power efficiency in AI workloads.
- Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces.
The ideal candidate will possess 10+ years of experience in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU/TPU-like architectures. Proficiency in Verilog/SystemVerilog RTL design and knowledge of GPU/TPU architectures are essential. Experience with AXI, NoC, or similar interconnect protocols is also required. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces is desirable.
What We Offer- A collaborative product development environment.
- The chance to work with a talented group of engineers from diverse backgrounds.
- A meritocratic workplace where individual contributions are valued.
- The opportunity to contribute to industry-shaping products from inception.
- The chance to learn from experienced professionals who have launched multiple successful semiconductor companies.
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