Digital Design Engineering Specialist

3 weeks ago


Bengaluru, Karnataka, India Analog Devices Full time
Job Responsibilities

As a Digital Design Engineering Specialist at Analog Devices, you will be responsible for designing key digital blocks such as accelerators and datapath IP in Verilog and SystemVerilog. This will involve creating built-in configurability to allow power/performance/area tradeoffs.

Main Responsibilities:

  • Develop a strong understanding of heterogeneous processor cores and subsystems, including A55/M55/M4/U55/RISC-V/DSP core and associated infrastructure.
  • Packaging digital IP for seamless integration into the design flow, including RTL/constraints/CDC waivers, timing wavers, DFT DRCs, and waivers.
  • Consolidating and curating digital IP for SPI/I2C/UART/JTAG and other slow serial interfaces and peripherals.
  • Evaluating 3rd party IPs on power/performance/area and other key qualitative aspects.
  • Building expertise on complex interfaces, peripherals, and protocols such as DDR, Ethernet, eMMC/SD, MIPI, Display Port, HDMI, PCIe, and high-speed D2D.
  • Developing and maintaining a catalog of digital IPs for ease of information sharing with customers across different BUs.
  • Creating user guides for RTL integration, synthesis, DFT, PnR, programming sequence, characterization, and other tasks.
  • Establishing evaluation flows for home-grown and 3rd party IPs for consistent benchmarking of evaluation.
Position Requirements

To excel in this role, you will require:

  • A minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science.
  • 2-6 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog.
  • Strong understanding of control path and data-path digital design concepts with an eye for realizing correct-by-construction solutions.
  • Experience with specifying design verification (DV) requirements, including test plans, coverage metrics, and evaluating DV quality.
  • Knowledge of lint, CDC, formal equivalence, DFT concepts, power analysis, and other relevant skills.
  • Experience with developing timing constraints and carrying out logic synthesis and static timing analysis.
  • Good interpersonal, teamwork, and communication skills to drive discussions with teams spread geographically.
  • Understanding of standard on-chip interfaces such as APB/AHB/AXI/Stream protocols is a strong plus.
  • Knowledge of processor/SoC architecture and/or DSP fundamentals is a strong plus.
  • Experience with end-to-end ASIC/SoC product development and productization is highly desirable.


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