Lead Analog Design Engineer with LIB Timing Expertise
3 weeks ago
BITSILICA seeks a highly skilled Lead Analog Design Engineer to join our team. This role requires expertise in LIB timing file generation, Verilog modelling, and analog design characterization using Cadence Spectre and Synopsys Hspice.
About the RoleThe successful candidate will be responsible for generating LIB timing files, creating Verilog models, and characterizing analog designs using industry-standard tools. Additionally, they will assist with analog quality checks, including EM/IR simulation.
RequirementsTo be considered for this position, applicants must possess strong skills in:
- LIB timing file generation
- Verilog modelling
- Analog design characterization (Cadence Spectre and Synopsys Hspice)
- EM/IR simulation
BITSILICA offers a competitive salary and benefits package to attract top talent. The estimated annual salary for this role is $120,000 - $150,000, depending on experience and qualifications.
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Lead Analog Circuit Designer
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Senior Analog Design Engineer
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Senior Analog Design Lead
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Senior Verification Engineer
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