
Senior Memory Compiler Specialist
2 weeks ago
We are seeking a highly skilled memory design professional to take on the role of lead designer.
The successful candidate will be responsible for developing memory compilers and Fast Cache instances, achieving outstanding Performance Power Area (PPA).
Key Responsibilities:
- Developing memory compilers and Fast Cache instances for next-generation Cores
- Understanding of computer architecture and concepts
- Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations
- Experience in design verification: Sense amplifier analysis, self-time analysis and marginality analysis
- Understanding of high-speed/low-power CMOS circuit design, clocking schemes, Static and complex logic circuits
- Understanding of Power versus Performance versus Area trade-offs in typical CMOS design
- Strong knowledge of physical implementation impact on circuit performance
- Good understanding of high-performance and low-power circuit designs with exposure to FinFet technologies, bit-cell stability analysis
- Proven experience as the designated responsible individual for a memory design, leading a small team of designers
- Expected to have good interpersonal skills
Requirements:
- Minimum 7 years of experience in SRAM/memory design margin, char, and related quality checks
- Some experience of working on Cadence or Synopsys flows
- Experience with Circuit Simulation and Optimization of standard cells
Candidate Profile:
- Strong technical skills in digital circuit design and verification
- Excellent problem-solving and analytical skills
- Good communication and teamwork skills
Benefits:
- Competitive salary
- Excellent benefits package
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