Advanced ASIC Design Professional
4 days ago
We are seeking an experienced Senior Physical Design Engineer to join our team.
">- Lead floor planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
- Expertise in low power techniques such as Voltage Islands, Power Gating, and substrate-bias for 65nm or lower node designs.
- Provide technical guidance and mentoring to Physical Design Engineers.
- Interface with front-end ASIC teams to resolve issues.
- Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
- Timing closure on DDR2/DDR3/PCIE interfaces.
- Effective communication skills.
- Strong background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
- Scripting languages expertise (PERL, TCL).
- Strong Physical Verification skill set.
- Static Timing Analysis in Primetime or Primetime-SI.
- Excellent written and oral communication skills. Ability to clearly document plans.
- Ability to interface with different teams and prioritize work based on project needs.
Qualifications:
Experience – 3 to 12 Years
Location:
Hyderabad
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