Advanced Mixed Signal Chip Synthesis Engineer

2 days ago

Mangalore, Karnataka, India beBeeEngineer Full time ₹ 1,50,00,000 - ₹ 2,01,00,000
Job Description:

Eteros Technologies is seeking a skilled engineer to lead the synthesis, static timing, and DFT efforts for an advanced mixed signal chip. This role will involve interfacing with various disciplines to ensure timely product delivery.

The ideal candidate will have thorough knowledge of ASIC design timing closure flow and methodology, as well as experience in STA tools and methodologies. They will also be familiar with low-power techniques, including clock gating, power gating, and millivoltage designs.

As a key member of our team, you will develop and maintain methodology and flows related to timing verification and closure. You will also analyze timing reports and utilize scripting techniques to drive rapid Eteros Technologies is seeking a skilled engineer to lead the synthesis, static timing, and DFT efforts for an advanced mixed signal chip. This role will involve interfacing with various disciplines to ensure timely product delivery.

The ideal candidate will have thorough knowledge of ASIC design timing closure flow and methodology, as well as experience in STA tools and methodologies. They will also be familiar with low-power techniques, including clock gating, power gating, and millivoltage designs.

As a key member of our team, you will develop and maintain methodology and flows related to timing verification and closure. You will also analyze timing reports and utilize scripting techniques to drive rapid results.

Key Qualifications:
  • BTech/MTech/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm
  • Knowledge of timing corners/modes and process variations
  • Knowledge of low-power techniques including clock gating, power gating, and millivoltage designs
  • Proficient in scripting languages (Tcl and Perl)
  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups
Responsibilities Include:
  • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
  • Develop and maintain methodology and flows related to timing verification and closure
  • Generation of block and full chip timing constraints
  • Analysis of timing reports and utilization of scripting techniques to drive rapid results
  • Support digital chip integration work and flows
What's in it for you:
  • Work on leading edge technologies
  • An opportunity for career development and growth
  • Competitive compensation
  • Medical Benefits and more

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