Principal Design Lead
6 hours ago
We are seeking a Senior RTL Principal Design Engineer to join our team.
The successful candidate will be responsible for designing and supporting the RTL of Interface Controller IP solutions.
Key responsibilities include working with existing RTL, adding new features, ensuring customer configurations are clean, and supporting customers in ensuring design cleanliness for LINT and CDC guidelines.
- Design and support of the RTL of PCIe/CXL/IDE/UALink IP solution.
- Work with the existing RTL, addition of new features into the RTL.
- Ensure various customer configurations are clean as part of verification regressions.
- Support customers, ensure design is clean for LINT and CDC design guidelines.
- BE/BTech/ME/MTech in Electrical / Electronics / VLSI with experience as a design and verification engineer.
- 8-16 years of core RTL Design experience using Verilog.
- System Verilog experience and UVM based environment usage/debugging required.
- PCIe/CXL/IDE experience needed. Prior experience in implementation of complex protocols must.
- Prior experience in IP development teams advantageous.
Scripting knowledge an advantage.
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