Senior Verification Lead
4 days ago
**Job Description:**
We are seeking an experienced verification engineer to lead verification efforts of complex IP subsystems based on the open-source RISC-V architecture.
The right candidate will have deep technical expertise combined with exceptional leadership skills and a proven track record in delivering complex projects.
**Responsibilities:**
- Lead end-to-end verification of complex IP subsystems partnering with architecture and design teams.
- Develop verification infrastructure components including test-benches, scoreboards, and stimulus generators.
- Develop and execute comprehensive verification plans for units and features.
- Implement functional coverage models.
- Debug designs in simulation, prototyping platforms, and silicon.
- Continuously drive methodology improvements to improve efficiency.
- Mentor junior engineers to build a high performing team.
**Minimum Qualifications:**
- Bachelors or Masters degree in electrical, computer engineering or related field.
- BS+8 years or MS+6 years of industry experience successfully delivering complex IP subsystems.
**Estimated Salary:** ₹20,00,000 - ₹30,00,000 per annum (dependent on experience).
Key Skills:
- SystemVerilog verification development experience.
- Testbench construction using UVM or analogous methodologies.
- Scoreboards and stimulus generators for complex units.
- Strong background in industry standards and protocols such as PCIe, Ethernet, CXL, AMBA AXI etc.
- Unit or feature ownership throughout the project lifecycle.
- Demonstrated team leadership experience with outstanding communication skills.
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