Senior Physical Design Engineer Lead for AI Hardware Innovation
7 days ago
This is a senior-level physical design engineer position that combines innovation and technical expertise to develop cutting-edge hardware for AI applications. The ideal candidate will have experience in designing and implementing complex systems-on-chip (SoCs) using advanced technologies such as 5nm/7nm and 14/16nm FINFET processes.
The role involves working closely with cross-functional teams, including system architects, SoC architects, IP developers, and RTL designers to ensure that the developed SoCs meet the required power, performance, and area goals. As a lead physical design engineer, you will be responsible for defining processes, methods, and tools for physical design and implementation of large complex SoCs.
Key responsibilities include owning all aspects of physical design implementation through synthesis, formal verification, floor planning, bus/pin planning, power domain implementation, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO, and sign-off. You will also work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and subsystem level.
Additionally, you will contribute to developing physical design methodologies, sign-off flows, and automation scripts using Tcl, Perl, or Python. Excellent collaboration and teamwork skills are essential to succeed in this role.
We offer a competitive salary package, estimated to be around $180,000 - $220,000 per annum, depending on experience. Benefits include comprehensive health insurance, retirement savings plan, and opportunities for professional growth and development.
BASIC QUALIFICATIONS:
BS + 10yrs or MS + 7yrs in EE/CS
10+ years of experience in all aspects of physical design implementation multiple tape-outs in FINFET technologies such as 5nm/7nm, 14/16nm.
Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation.
Must have good communication and analytical skills.
PREFERRED QUALIFICATIONS:
Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
Thorough knowledge of device physics, custom/semi-custom implementation techniques.
Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc.
Experience in extraction of design parameters, QOR metrics, and analyzing trends.
Experience with DFT & DFM flows.
Experience leading top level of SoC and all integration issues between IPs and partitions, drive package requirements, resets/clocks and power detection at SoC level
Ability to provide mentorship, guidance to junior engineers and be a very effective team player.
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