Senior Analog Mixed Signal Validation Expert

23 hours ago

Vellore, Tamil Nadu, India beBeeVerification Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Job Description:

We are seeking a skilled Lead AMS Verification Engineer to lead the planning, development, and execution of verification strategies for analog/mixed-signal IPs and SoCs.

Main Responsibilities:

  • Define and implement verification plans, including testbenches, stimulus generation, and checking strategies.
  • Develop and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments.
  • Perform co-simulation of analog/digital designs using industry tools (e.g., Cadence, Synopsys, Siemens EDA).
  • Conduct mixed-signal simulations, behavioral modeling of analog blocks, and integration into top-level environments.
  • Collaborate with analog designers to create AMS behavioral models (e.g., Verilog-A/AMS) for early integration and verification.
  • Debug complex AMS simulation issues across multiple abstraction levels.
  • Drive coverage analysis and sign-off using functional, formal, and assertion-based methods.
  • Mentor and guide junior engineers in best practices, methodologies, and tool usage.
  • Ensure verification deliverables meet project timelines and quality standards.

Requirements:

  • Minimum 8+ years of hands-on AMS verification experience in IP/SoC projects.
  • Proven track record in building verification environments using SystemVerilog, Verilog-AMS, or UVM.
  • Strong background in mixed-signal simulation and behavioral modeling.

Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

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