
Senior Verification Expert
2 weeks ago
Job Title: Senior Design Verification Engineer
We are seeking a talented professional to drive verification closure and collaborate with cross-functional teams.
The ideal candidate will have 5+ years of experience in SoC/IP level verification, with expertise in SystemVerilog, UVM methodology, testbench development, functional coverage, assertions, and debugging.
A strong understanding of AXI/APB bus protocols and exposure to high-speed interfaces (USB, Ethernet, DDR, etc.) is highly desirable.
Key Responsibilities:
- Lead verification efforts for complex digital designs
- Develop and maintain testbenches and simulation environments
- Drive functional coverage and assertion-based verification
- Collaborate with hardware and software teams to ensure seamless design implementation
- Participate in root cause analysis and defect fixing
Requirements:
- 5+ years of experience in Design Verification
- Hands-on expertise with SystemVerilog/UVM
- Experience in PCIe / Formal Verification / Wireless (any one is a strong advantage)
- Strong understanding of SoC/IP level verification
- Knowledge of AXI/APB protocols and high-speed interfaces
- Proficiency in simulation, regression, and coverage closure
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