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ASIC Design Test Engineer
2 weeks ago
At our organization, we are seeking a seasoned ASIC Design DFT engineer with expertise in JTAG & IJTAG protocols, MBIST and scan architectures.
The ideal candidate should possess strong knowledge of memory testing and silicon engineering trends. Additionally, they should have experience in implementing hardware Memory BIST features that support ATE, in-system test, debug, and diagnostics needs of memories in design.
Key Responsibilities:
- Implement Memory BIST features to meet ATE, in-system test, debug, and diagnostics requirements for memories in design.
- Collaborate with cross-functional teams including design, design-verification, and backend teams to integrate and validate test logic throughout the design and implementation flow.
- Design and debug test patterns with minimal supervision.
- Release high-quality test patterns to the test team and provide support during silicon bring-up and yield improvement initiatives.
Requirements:
- Strong understanding of state-of-the-art trends in memory testing and silicon engineering.
- Hands-on experience with JTAG & IJTAG protocols, MBIST, and scan architectures.
- Verification skills including System Verilog, LEC, and validating test timing of designs.
- Experience working with gate-level simulations and debugging with VCS and other simulators.
- Knowledge of System Verilog testbenches and UVM/VMM frameworks.
- Post-silicon validation and debug experience, ability to work with ATE patterns.
- Excellent verbal communication skills and ability to thrive in a dynamic environment.
- Proficiency in scripting languages such as Python or Perl.
